Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 556564
Job Posting Title: Engineer, Principal- IC Design – Physical Design
City: Irvine
State: California
Country: USA
Alternate Location: N/A
Percent of Travel Required: 0%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
Broadcom has led the industry migration from legacy 10/100 Fast Ethernet (FE) to Gigabit Ethernet in PCs and servers and continues to strategically invest in leading edge Ethernet technology, affording Broadcom’s continued market leading success through first-to-market features, software consistency, and world-class reliability and stability.
RESPONSIBILITIES:
• Ownership of design floor planning, synthesis, place and route, clock and power distribution, static timing analysis, signal integrity analysis & physical verification.
• Mentors/Directs physical design activities of less experienced engineers.
Requirements:
Experience required is typically a BSEE degree and 12 years of experience, an MSEE degree 9 and years of experience or a PhD EE and 6 years of experience or equivalent.
• This position requires an understanding of RTL to GDS flows, timing analysis, CMOS device operation and advanced layout rules.
• 10+ years directly related physical design expertise in state of the art ICs with emphasis on VLSI physical design and methodology on 28 nanometer process nodes.
• Must have a proven track record of delivering tape-out quality GDSII with silicon success.
• A solid understanding of digital circuit design and Verilog.
• Able to analyze static timing paths for high speed digital blocks, and implement design fixes to meet block frequency target.
• Basic understanding for circuit design of custom macro blocks such as RAMs, Register Files, CAMs, high-speed IO drivers and other IP cells.
• Power user of place and route tools such as Atoptech, ICC, Magma or Cadence SOCe
• Strong hands on familiarity with Design Compiler, Calibre, Hspice, LEC, Formality, Primetime SI, Redhawk and StarRC preferred.
• Strong scripting in Perl and TCL.
• Self Motivator and excellent problem solving skills.
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