Entry level Verification / Modeling Design Engineer (Irvine, CA, US, 92617-3038)


Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.



Job Req ID: 556521 



Job Posting Title: Entry level Verification / Modeling Design Engineer



City: Irvine



State: California



Country: USA



Alternate Location: US – California, Southern – Irvine



Percent of Travel Required: 0% – 25%



Job Function: Engineering



Discipline: ENG-Hardware-IC Design






 



We are seeking digital design/verification engineer for Radio Modeling group. This opportunity will expose the engineer to various wireless standards (WiFi, Bluetooth, NFC, ZIG). This is an exciting opportunity to get involved in ASIC design/verification cycle. Write simple behavioral models of analog circuits in SystemVerilog. Additional work includes writing test benches for top level blocks and tests to verify the top level block meets specifications.






 






Candidate will be responsible for the following tasks. Modeling analog and RF behavior using the SystemVerilog language. Support various tools such as Spectre, VerilogAMS, Ncsim/irun/vcs, and Modelism. Write programs in Python and TCL. Manage radio projects from definition, verification, bring up and ATE. Write synthesizable verilog RTL for digital circuits in radio. Provide verification for digital IP blocks. Work on top level Radio verification and simulations. Implement verification for digital IP blocks. Generate top level Radio verification and simulation states.






 






The job requires a background in digital design including a strong ability to code in Verilog or SystemVerilog. A background in systems or in DSP is a plus. Familiarity with Verilog simulators like irun or VCS also a plus. Additionally, knowing scripting languages like Python and tcl are helpful. Candidates must be able to communicate effectively with engineers of all disciplines in a fast-paced and cross-functional environment.






Minimum education is Master’s degree, or foreign equivalent, in Electrical Engineering or related.






Special skills include experience or background in analog circuits, Verilog Simulators/Modeling, Cadence’s Virtuoso, and digital simulator NCSIM/IRUN/VCS.



Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)





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