Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 556570
Job Posting Title: Principal Physical Design Engineer
City: San Diego
State: California
Country: USA
Alternate Location: N/A
Percent of Travel Required: 0% – 25%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
Responsibilities:
As a member of our Broadcom Mobile and Wireless organization, you will part of a design team implementing the latest advances in Bluetooth EDR, Near field communications (NFC), and the broadest line of Wi-Fi® integrated circuits in the industry.
As an IC Physical Design Engineer, you will be responsible for 40nm/28nm/20nm physical digital design implementation for low power designs. As an engineer with STA/timing closure focus, you will be responsible understanding design timing intent, constraints development, validating multimode constraints and ensuring design meets performance, power and area goals. You will also contribute in the area of RTL to GDS low power design implementation with a focus on both the front-end and back-end. You will participate in block and chip level physical design, developing and executing synthesis, DFT, static timing analysis, Place/Route, and power analysis flows.
Requirements:
– Typically requires a BSEE/CE degree and 12 years of experience or MSEE/CE degree and 9 years of experience or a PhD and 6 years of experience
– Excellent knowledge of Static Timing Analysis (STA) tools like Primetime and Timing Closure methodology development and implementation is required
– Excellent knowledge of digital circuit design and physical design methodologies such Place and Route, IR/EM Power Analysis, Clock Tree Synthesis
– Strong collaboration with RTL design team, understanding of Verilog/VHDL and drive design intent closure is required
– Strong expertise in flow and infrastructure development for timing closure of block and SOC level is required
– Strong understanding of DFT flow is required
– Strong analytic and problem solving skills
– Strong verbal and written communication skills
Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)
Nearest Major Market: San Diego
Job Segment:
Semiconductor, Network, Engineer, Design Engineer, Embedded, Science, Technology, Engineering
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