Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 549465
Job Posting Title: Sr. Staff Chip Integration Engineer
City: San Jose
State: California
Country: USA
Alternate Location: N/A
Percent of Travel Required: 0%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
The Network Switch Group at Broadcom has brought some of the most complex and cutting edge networking ASIC’s and multi-chip solutions to market over the last decade. The group develops ASIC’s for L2/L3 switch routing. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several Terabits/sec. These networking ASIC’s support a large number of ports ranging from 10/100Mb/s, 1Gb/s, 10Gb/s, 40Gb/s and 100Gb/s speeds as well as various line interfaces and protocols.
We are looking for bright, motivated and hardworking engineer with leadership potential to join our top notch chip design engineering team.
As a chip integration lead you will work closely with software, emulation, block level design, verification, DFT, physical design and IP teams through a chip development cycle from architecture to tapeout, and through silicon validation process. This ASIC SOC will be at the fore front of the next technology node for both Infrastructure Networking Group (ING) and Broadcom. You will participate in driving cutting edge VLSI issues, IP specification and validation of all network switch related IPs. This ASIC pushes the performance limit for our physical design and timing closure methodology.
The candidate will be part of Infrastructure and Networking team at Broadcom. He/she will own the chip level RTL and manage block level and project related cross functional deliveries. He/She will be exposed to state of the art chip development tools and ASIC flow. Responsibility includes:
- Document Micro-architecture and design specification, board specifications
- Full chip integration with high speed SerDes, different I/O interfaces , high speed clocking
- Learn to work closely internal IP developers to work through early design functionality and integration requirements
- RTL coding, Synthesis, Floor-planning analysis, timing closure with physical design team
- Top-level design validation testing support to our design verification and emulation team
- Participate in layout, package, system board , ATE board and burn-in board reviews
- Silicon bringup plan preparation and execution
- Define IP validation plan and lead the silicon validation team (DFT team, ATE team, PVT team and EVT team) to execute
Job Requirements
- Typically requires a BS degree and 9-12 years of experience, an MS degree and 6-9 years of experience or a PhD and 3-6 years of experience or equivalent
- Experience with Verilog coding for top-level IC design
- Must have good RTL experience including design specification, timing requirements, verification, and synthesis. Must have strong UNIX-based EDA tool skills and knowledge of ASIC design flows
- Working knowledge of design validation; a plus to have experience building System Verilog test benches and infrastructure and performing chip-level validation
- Working knowledge of advanced technology notes (20nm, 16nm, 10nm)
- Knowledge of IP integration (standard cells, IO’s, memory and Analog IP)
- Exposure to cross clock domain issues and resolutions
- Exposure to package and board level issues.
- Hands on experience with logic synthesis, Static timing analysis, P&R and logic equivalence checking.
- VLSI knowledge and memory design is a plus
- Excellent written and verbal communication skills
Efficient in following skills:
- Verilog coding and Lint tools
- Synthesis using Synopsys tool suite
- Timing Analysis using Synopsys Primetime tool
- Formal Verification
- DFT concepts of Scan, BIST.
- Strong Perl and Tcl scripting skill
Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)
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Semiconductor, Engineer, Network, Embedded, Design Engineer, Science, Engineering, Technology
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