Principal level ASIC Design Engineer (Irvine, CA, US, 92617-3038)



Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.



Job Req ID: 549881 



Job Posting Title: Principal level ASIC Design Engineer



City: Irvine



State: California



Country: USA



Alternate Location: US – California, Southern – Irvine



Percent of Travel Required: 0%



Job Function: Engineering



Discipline: ENG-Hardware-IC Design






 



The candidate will be responsible for ASIC design and implementation of various RF-centric digital functions associated with current and next generation radio products. The candidate will work within the systems development team and closely with RF engineering team to develop and implement digital and DSP blocks related to radio operation and performance. Some of the job responsibilities are: develop spec documents, design and implement digital and DSP blocks, develop verification platforms, perform simulations, and solve integration and testing problems during the development, characterization, and production stages of the product. Successful candidate must have the ability to communicate with engineers of varying backgrounds: systems, hardware, RFIC design, and verification.






 






  • Typically requires a Master degree and 9+ years of experience or a PhD with 6+ years of experience, in VLSI/ASIC design or ASIC implementation.


  • Extensive experience with RTL programming languages.


  • Experience with verification methodologies and tools and advanced complex RTL/C test-bench developments.


  • Experience with developing algorithms in C, C++ is a plus


  • Experience with scripting language such as Perl, Python.


  • Good understanding of Matlab/Simulink modeling is a plus


  • Experience in the design of DSP ASIC architectures with a good understanding of hardware/firmware partitioning, and multi-clock domain implementations.


  • Must have experience with lab testing and characterization of digital sub-systems.


  • Candidate must have good communication skills with willingness to interact with various groups within the company.


  • Experience with physical design flows, tools, methodologies, and development of timing constraints is a plus.


  • Familiarity with flows and tools for co-simulation of RTL and C models is a plus.


  • Familiarity with testing and integration of RF and baseband systems in the lab is a plus.


  • Experience with implementation of calibration modules for RF/Analog blocks is a plus.

Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)





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