Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 387
Job Posting Title: Engineer, Sr Staff- IC Design
City: Irvine
State: California
Country: USA
Alternate Location: India – Bangalore
Percent of Travel Required: 0% – 25%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
Join the Residential Broadband IP design team which is responsible for the design, verification, and integration of multimode cellular modem within the Broadband Communication Group. The modem IP team designs modem HW for all 3GPP protocols. We have number of junior to senior level openings for the LTE L1 HW accelerator design.
As cellular modem HW accelerator designer you work with system algorithm and SW teams to specify modules to complete data paths. Collaborate with architects to translate the functional requirements into micro architectural specification , implement the HW, verify and deliver for modem IP integration.
Requirements
Master’s Degree or above in Wireless communication, Signal Processing, embedded systems or electronics. Minimum of 3 years of experience in ASIC/SoC front-end (preferably RTL VHDL based) design and methodologies. Earlier experience with embedded systems and SoC HW architectures is desierable. Natural talent for discussing and analyzing design and verification concepts and dilemmas with colleagues and specialists. Good presentation skills. Self-driven and capable for independent work and independent decision making.
• Solid understanding on wireless communication and related digital signal processing fundamentals.
• Knowledge and frontend design experience in GSM, WCDMA or LTE standards is highly desirable.
• High-speed DSP data path design experience such as digital filters, FFTs, complex MIMO receivers and error-correction decoding, etc.
• Ability to understand and analyze key performance indicators of such designs in terms of latency, through put, power and area.
• Hands on front-end design of complex multi clock domain blocks and soft IP delivery methodologies.
• Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
• Familiarity with scripting languages (Perl, TCL, Python etc.).
• Appreciation for low power ASIC / SoC design & implementation techniques in the latest technology nodes.
• Self-reliant with can do attitude.
• Capable of being accountable for own work as well as working effectively in a team.
As a key member of the modem IP team you will:
• Master the existing multimode 2G, 3G & LTE L1 HW accelerator subsystems.
• Support integration of these existing L1 HWA subsystems at modem IP and chip level.
• Assist in debugging and resolving any issues that come up in simulation regressions.
• Debug and resolve pre/post silicon lab failures.
• Analyze reported issues, evaluate new requirements and determine the proper resolution tracking to completion.
• Eventually own the chosen modules and data paths for all modem IP releases and chip integrations.
• Involve in design and development of future 3GPP release 12, 13 compliant modem IP and it’s subsystems, including the MTC category.
Join the Residential Broadband IP design team which is responsible for the design, verification, and integration of multimode cellular modem within the Broadband Communication Group. The modem IP team designs modem HW for all 3GPP protocols. We have number of junior to senior level openings for the LTE L1 HW accelerator design.
As cellular modem HW accelerator designer you work with system algorithm and SW teams to specify modules to complete data paths. Collaborate with architects to translate the functional requirements into micro architectural specification , implement the HW, verify and deliver for modem IP integration.
Requirements
Master’s Degree or above in Wireless communication, Signal Processing, embedded systems or electronics. Minimum of 3 years of experience in ASIC/SoC front-end (preferably RTL VHDL based) design and methodologies. Earlier experience with embedded systems and SoC HW architectures is desierable. Natural talent for discussing and analyzing design and verification concepts and dilemmas with colleagues and specialists. Good presentation skills. Self-driven and capable for independent work and independent decision making.
• Solid understanding on wireless communication and related digital signal processing fundamentals.
• Knowledge and frontend design experience in GSM, WCDMA or LTE standards is highly desirable.
• High-speed DSP data path design experience such as digital filters, FFTs, complex MIMO receivers and error-correction decoding, etc.
• Ability to understand and analyze key performance indicators of such designs in terms of latency, through put, power and area.
• Hands on front-end design of complex multi clock domain blocks and soft IP delivery methodologies.
• Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
• Familiarity with scripting languages (Perl, TCL, Python etc.).
• Appreciation for low power ASIC / SoC design & implementation techniques in the latest technology nodes.
• Self-reliant with can do attitude.
• Capable of being accountable for own work as well as working effectively in a team.
As a key member of the modem IP team you will:
• Master the existing multimode 2G, 3G & LTE L1 HW accelerator subsystems.
• Support integration of these existing L1 HWA subsystems at modem IP and chip level.
• Assist in debugging and resolving any issues that come up in simulation regressions.
• Debug and resolve pre/post silicon lab failures.
• Analyze reported issues, evaluate new requirements and determine the proper resolution tracking to completion.
• Eventually own the chosen modules and data paths for all modem IP releases and chip integrations.
• Involve in design and development of future 3GPP release 12, 13 compliant modem IP and it’s subsystems, including the MTC category.
Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)
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