Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 549841
Job Posting Title: Engineer, Principal- IC Design – Physical Design
City: San Jose
State: California
Country: USA
Alternate Location: US – California, Southern – Irvine
Percent of Travel Required: 0% – 25%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
The industry’s most respected fabless communications semiconductor, software and systems innovator, Broadcom, is looking for the world’s best and brightest engineers.
As one of Fortune magazine’s “Most Admired Companies”, Broadcom promotes an open work environment, embracing change, taking risks and doing the impossible every day. Outstanding initiative and aggressive execution is at the core of who and what we are, and we take pride in outdoing, outsmarting and outselling the competition. With the fifth most valuable patent portfolio in the world and through the hard work and dedication of our people, Broadcom achieves a leadership position in every market we enter. With our culture of innovation rewarding brainpower and risk taking with industry-leading company ownership/benefits and competitive salary, this unique environment creates enormous opportunity for you.
Come leverage Broadcom’s world-class talent and technology and make the impact in network high-speed interconnect product (HSIP) Optical semiconductors that you have always wanted to accomplish, with a team that you can count on. Join Broadcom and become the best engineer you can be.
This position is for the physical ASIC design with a group of block level physical designers interacting with logic designers of high-speed Enterprise networks.
In this role you will own top level or block level apects of the process from netlist handoff to tapeout: floorplanning, place and route, timing and power closure and physical verification.
At chip level you will provide die size estimation studies and resource and schedule planning.
Requirements:
– Typically requires a BS degree and 12 years of experience or an MS degree and 9 years of experience or a PhD and 6 years of experience
– 6+ years experience developing high performance communications/networking ASIC products.
– Should be comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation.
– Experience in major Place & Route tools is required
– Familiar with ASIC standard cell logic and physical libraries, experience in DRC/LVS and tapeout procedures
– Experience using Primetime/ PT-SI timing analysis and noise analysis for chip signoff a plus
– Experience using Apache (or other equivalent tools) dynamic power analysis for chip signoff is a plus
Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)
Job Segment:
Semiconductor, Network, Engineer, Design Engineer, Embedded, Science, Technology, Engineering
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