Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 547033
Job Posting Title: Sr. ASIC Design Engineer (DDR PHY)
City: Andover
State: Massachusetts
Country: USA
Alternate Location: N/A
Percent of Travel Required: 0% – 25%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
Join Broadcom’s Broadband Communications Group (BCG), a world-class team responsible for designing and supporting some of the coolest products in millions of homes and businesses around the world. We enable residential broadband services, cable, satellite, and IP set-top boxes. BCG prides itself on being the dominant player, both in emerging and developed markets. If you have a passion for advancing technology, we encourage you to apply for this exciting opportunity.
As part of the DDR PHY team you will implement, model, and verify a high speed DDR physical layer interface for our next generation products. You must have good working knowledge of high-speed chip design in both digital logic and circuit aspects. You should have strong working knowledge in the DDR interface and DRAM interface technology and has demonstrated experience on DDR3 or DDR4 starting from definition to successful silicon characterization and production. You should have good knowledge and experience working with verification test benches and working collaboratively to verify correct logical functionality. Having knowledge of high speed SERDES, PLL, high speed IO, and packaging is a plus. You should have good understanding of high speed clocking and power distribution issues in I/O designs, integration, and internal/external timing closure using static timing analysis tools. Knowledge of ASIC design flows is a plus. You should possess high motivation & good team work.
Essential Duties and Responsibilities include:
• Defining the architecture of the physical layer & publish the micro-architecture specifications
• Developing RTL for a DDR PHY
• Planning the physical architecture of the PHY
Required:
• The minimum job requirement for this position is BSEE and 15+ years of experience
• Experience with high speed digital design and high speed clocking
• Experience with RTL simulators and waveform viewers
• Experience working collaboratively with verification engineers
• Verilog language and associated RTL design and simulation tools
• ASIC design flow (synthesis, static timing, etc.)
• General Linux environment tools
• Good communication skills
• Candidate must be a self-starter and able to work independently
Recommended:
• Experience with lint and equivalency checking tools
• Emulation experience
• Familiarity with latest DDR DRAM standards
*Please note actual Job Title will be determined by education and years of experience
Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)
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