Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.
Job Req ID: 547143
Job Posting Title: Sr. ASIC DFT Engineer
City: Santa Clara
State: California
Country: USA
Alternate Location: N/A
Percent of Travel Required: 0% – 25%
Job Function: Engineering
Discipline: ENG-Hardware-IC Design
You will contribute to the development of complex SOC/ASIC and responsibilities will include:
– Top-level DFT plan and integration
– ATPG & ATE interface
– ATE bring-up & failure analysis
– Test time reduction
– Synthesis
– STA & Simulation for DFT mode
– Formal verification
– Multi-Power domain implementation
– DFT problem solving
– DFT Flow improvement
Requirements:
– Typically requires BS degree and 12 years of experience or MS degree + 9 years of experience
– Extensive DFT background with multiple years hands on experience
– Chip level DFT plan and integration ability
– Deep knowledge about DFT including LBIST(At-Speed SCAN), ATPG, MBIST, JTAG
– Test time reduction skill
– Solid understanding of Low power DFT, Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models
– Experience with silicon failure analysis and debugging
– Solid understanding of STA
– Simulation skill for DFT with timing
– Familiarity with ASIC/SOC design flows & methodology- Low power, multi-power domain and mixed-signal design
– Good knowledge of EDA tools. Experience with Mentor DFT tools
Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)
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