Staff II- IC Design Engineer


Broadcom Corporation (NASDAQ: BRCM), a FORTUNE 500® company, is a global leader and innovator in semiconductor solutions for wired and wireless communications. Broadcom® products seamlessly deliver voice, video, data and multimedia connectivity in the home, office and mobile environments. With the industry’s broadest portfolio of state-of-the-art system-on-a-chip and embedded software solutions, Broadcom is changing the world by Connecting everything®.



Job Req ID: 551802 



Job Posting Title: Staff II- IC Design Engineer



City: San Jose



State: California



Country: USA



Alternate Location: US – California, Northern – Bay Area; US – California, Southern – Irvine



Percent of Travel Required: 0% – 25%



Job Function: Engineering



Discipline: ENG-Hardware-IC Design






 



As a Staff II Physical Design Engineer, the ideal candidate will be responsible for the 16nm high speed physical designs. You will gain valuable skills as you are trained in: establishing and implementing a hierarchical design flow and signoff process and the application and use  physical design tools available from Synopsys , Cadence, Mentor, Atoptech; and to understand, review physically close DRC’s at the block.









You will be challenged with responsibilities including:



floorplanning; place and route; timing; power closure and physical verification



You will start with block level design and ramp up to future chip level design



Responsibility/ownership of block level physical implementation for production quality 16nm designs



Establish timing constraints



Review timing reports



Physically close timing at the block and top level



Add-on knowledge of synthesis/STA and DFT will be a plus






 






Job Requirements



BE plus 5 years, or ME plus 3 years,  in deep-sub-micron IC physical designs, or equivalent experience



Experience in major P&R tools is required, such as ICC, ATopTech AP, Synopsys ICC or Cadence SOC Encounter



Experience with 28nm or below technology



Physical verification closure (physical closure tools knowledge)



Familiar with ASIC standard cell logic and physical libraries and experience in DRC/LVS (Caliber preferred) and tapeout procedures



Experience using Primetime timing reports and timing closure procedures with backend place and route tools and design for power (Apache or other power design tools)



Experience using Apache (or other equivalent tools) dynamic power analysis for chip signoff is a plus



Experience with TCL and Perl, to achieve higher productivity, is desired



Broadcom is an equal opportunity employer (Minorities/Females/Disabled/Veterans)





Job Segment:
Semiconductor, Network, Engineer, Embedded, Design Engineer, Science, Technology, Engineering


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