Senior with major in Electrical engineering, computer engineering or related major. Graduate student preferred. 2. Must have taken courses in logic design and synthesis, computer architecture and organization as well as VLSI design. 3. Must have done lab projects related to logic design using schematic entry tools or Verilog RTL language. 4. hands-on logic design experience using Verilog, RTL simulation, STA, timing fix, lint and version control tools is highly desirable. 5. Technical documentation skills using commercial office tools is a must. 6. Good team work spirit and communication skill. Willing to learn. Description: Logic design engineer Focus on ASIC implementation of algorithms, control modules and SoC integration. Qualifications MSEE or PhD EE in progress. |
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Thou marvell’st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data…
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